FIT2069 Computer architecture - Semester 1, 2012

This unit covers the internal mechanism of computers and how they are organised and programmed. Topics include combinatorial and sequential logic, Boolean Algebra, Karnaugh maps, counters, ripple adders, tree adders, memory/addressing, busses, speed, DMA, data representation, machine arithmetic, microprogramming, caches and cache architectures, virtual memory and translation look-aside buffers, vectored interrupts, polled interrupts, pipelined architecture, superscalar architecture, data dependency, hazards, CISC, RISC, VLIW machine architectures.

Mode of Delivery

Clayton (Day)

Contact Hours

2 hrs lectures/wk, 3 hr laboratory/fortnight, 2 hr tutorial/fortnight

Workload

• Lectures: 2 hrs per week
• Laboratory: 3 hrs per fortnight
• Tutorial: 2 hrs per fortnight

This is a technically oriented unit where content in any given week depends strongly on content in preceding weeks. Therefore students should plan and commit a minimum of 8 to 12 hours for personal study every week and should allocate up to 5 hours per week in some weeks for use of a computer. Laboratory work will require preparation before attendance.

The unit content requires a strong focus on understanding content through the semester.

Unit Relationships

Prerequisites

FIT1031 or FIT1001 and FIT1008 or FIT1015

Chief Examiner

Campus Lecturer

Academic Overview

Outcomes

At the completion of this unit students will have -
A knowledge and understanding of:

• combinatorial and sequential logic, Boolean Algebra, Karnaugh maps, and hazards;
• counters, ripple adders, tree adders, memory/addressing, computer busses, logic and bus speed, and Direct Memory Access;
• data representation for integers and floating point operands;
• machine arithmetic, microprogramming;
• storage herarchies, caches and cache architectures, performance impact of caching;
• virtual memory and translation look-aside buffers, performance impact of TLB caching;
• vectored and polled interrupt handling;
• pipelined architecture, superscalar architecture, data dependency, and hazards;
• CISC, RISC, VLIW machine architectures.

Developed the skills to:

• model combinatorial and sequential logic circuits using a simulator tool;
• perform programming tasks in assembly code.

Graduate Attributes

Assessment Summary

Examination (3 hours): 60%; In-semester assessment: 40%

Assessment Task	Value	Due Date
Laboratory Exercises	Total 30% (5% each)	In weeks 2, 4, 6, 8, 10 and 12
Tutorial Exercises	Total 10% (1.667% each)	In weeks 1, 3, 5, 7, 9 and 11
Examination 1	60%	To be advised

Teaching Approach

• Lecture and tutorials or problem classes
  This teaching and learning approach provides facilitated learning, practical exploration and peer learning.
• Laboratory-based classes
  This teaching approach is practical learning.

Feedback

Our feedback to You

• Informal feedback on progress in labs/tutes
• Test results and feedback

Your feedback to Us

Previous Student Evaluations of this unit

Based on extensive student feedback in Sem 1 2011 more tutorial time was requested. Fortnightly tutorials are now 2 hours (up from one hour).

Recommended Resources

Logisim software (free)

Xspim/Spim software (free)

Examination material or equipment

Non-programmable scientific calculators will be permitted.

Unit Schedule

Week	Activities	Assessment
0		No formal assessment or activities are undertaken in week 0
1	Intro/History/Background; Boolean Algebra	Tutorial 1
2	Karnaugh maps, Hazards; Data Representation	Laboratory 1
3	Counters, Adders, Shifters, Sequential Logic	Tutorial 2
4	Basic Machine Organisation	Laboratory 2
5	Control Unit Design	Tutorial 3
6	Instruction Sets and Design	Laboratory 3
7	I/O, Interrupts, DMA	Tutorial 4
8	Cache Organisation	Laboratory 4
9	Mass Storage/Memory Management	Tutorial 5
10	CPU Organisation/Pipelined Architectures	Laboratory 5
11	Superscalar Architectures	Tutorial 6
12	CISC, RISC, VLIW, Other Machine Architectures	Laboratory 6
	SWOT VAC	No formal assessment is undertaken SWOT VAC
	Examination period	LINK to Assessment Policy: http://policy.monash.edu.au/policy-bank/ academic/education/assessment/ assessment-in-coursework-policy.html

*Unit Schedule details will be maintained and communicated to you via your MUSO (Blackboard or Moodle) learning system.

Assessment Requirements

Assessment Policy

Faculty Policy - Unit Assessment Hurdles (http://www.infotech.monash.edu.au/resources/staff/edgov/policies/assessment-examinations/unit-assessment-hurdles.html)

Assessment Tasks

Participation

There are 6 Tutorial Exercises each worth 1.667% of the total mark (assessed).

There are 6 Laboratory Exercises each worth 5% of the total mark (assessed, preparation required).

Tutorials and Laboratories are scheduled in alternating weeks.

Attendance is expected and strongly recommended.  This unit is tightly integrated so if students miss a Tutorial or Laboratory they will have difficulty understanding later material.

• Assessment task 1

  Title:

  Laboratory Exercises

  Description:

  6 Laboratory Exercises. Individual assessment per task. Preparation required.
  
  Attendance is expected and strongly recommended.  This unit is tightly integrated so if students miss a Laboratory they will have difficulty understanding later material.

  Weighting:

  Total 30% (5% each)

  Criteria for assessment:

  The criteria used to assess laboratory tasks are:

  1. All programs must assemble and execute correctly. Evidence of testing is required.
  2. Programs must meet the problem specification.
  3. Assembly code should be readable and maintainable.
  4. Programs should be documented.
  5. All algorithms should follow the style presented in laboratory examples and be correct.
  6. Logic simulator circuits must comply with the specified truth table or other functional definition.

  Due date:

  In weeks 2, 4, 6, 8, 10 and 12

• Assessment task 2

  Title:

  Tutorial Exercises

  Description:

  6 Tutorial Exercises. Individual assessment per task.
  
  Attendance is expected and strongly recommended.  This unit is tightly integrated so if students miss a Tutorial they will have difficulty understanding later material.

  Weighting:

  Total 10% (1.667% each)

  Criteria for assessment:

  The criteria used to assess submissions are:

  1. Correctness and understanding - there may be more than one "right" answer in many cases. We will look for answers that reflect understanding of the underlying principles and theories.
  2. Completeness - that you have answered all parts of each question.
  3. Presentation - that you have presented your answers in a suitably formatted style.
  4. Use of evidence and argument - you are able to explain your position by using logical argument drawing on the theory presented in the unit.

  Due date:

  In weeks 1, 3, 5, 7, 9 and 11

Examinations

• Examination 1

  Weighting:

  60%

  Length:

  3 hours

  Type (open/closed book):

  Closed book

  Electronic devices allowed in the exam:

  Non-programmable scientific calculators will be permitted.

Assignment submission

Online submission

If Electronic Submission has been approved for your unit, please submit your work via the VLE site for this unit, which you can access via links in the my.monash portal.

Extensions and penalties

Returning assignments

Other Information

Policies

Student services

Reading list

Recommended Reading:

William Stallings, Computer Organization and Architecture: Designing for Performance, 8/E, Prentice Hall, ISBN-13: 9780136073734

Morris Mano and Charles Kime, Logic and Computer Design Fundamentals 4/E, Pearson Prentice Hall, ISBN 0-13-140539-X

Supplementary Recommended Reading:

http://www.csse.monash.edu.au/~carlo/SYSTEMS/